A board can pass every visual review and still fail at the fabricator, because the design rules never matched the process or because the Gerber package described a stack-up nobody quoted. KiCad gives engineers a complete path from schematic to production data, but it does not decide which clearances, drill sizes, or layer stack a project actually needs. That judgment stays with the designer. The two disciplines that carry the most weight at handoff are design-rule checking and manufacturing-file generation, and both deserve attention long before the final DRC run.
Configuring Design Rules Before the First Trace Is Routed
KiCad separates two verification layers, and confusing them causes unnecessary rework. The Electrical Rules Checker works on the schematic and flags unconnected pins, conflicting outputs, and invalid electrical connections. The Design Rules Checker works on the board and tests geometry against configured clearances, track widths, drill rules, and connectivity requirements. Run ERC first. A PCB inherits its netlist from the schematic, so a schematic error that slips through will appear later as a confusing board-level violation.
Default design rules are deliberately generic. A production project needs its own net classes, with widths, spacing, and via definitions assigned to power rails, high-speed signals, and differential pairs rather than applied uniformly to everything. A dependable kicad workflow treats the design-rule file as a living specification rather than a leftover default, because every check the DRC performs is only as meaningful as the numbers behind it.
Before routing begins, define the project inputs that drive those numbers: board outline and maximum dimensions, number of copper layers, nominal board thickness such as 1.6 mm, copper weight such as 35 µm outer copper, minimum trace width and spacing, minimum drill and finished-hole sizes, the required surface finish, and any controlled-impedance nets. These are project decisions, not universal constants. The final values must satisfy both the component requirements and the documented capability of the fabricator who will build the board.
That last point is where optimistic rule sets go wrong. Some fabricators publish minimum trace and spacing down to 0.002″, impedance control tolerance of ±5%, back drilling with a minimum hole size of 15.7 mils and depth tolerance of ±6 mils, heavy copper up to 30 oz, and constructions up to 58 layers. Those are capability ceilings, not targets. Setting a board to the tightest available limit raises cost and reduces the process window for no electrical benefit. Enter tighter values only where the circuit genuinely needs them, and confirm each one against the specific fabricator’s published data before the rule is written into the project.
Working Through DRC Results Without Suppressing Real Problems
A finished layout typically produces a long list of markers: clearance violations, hole-to-hole spacing, courtyard overlaps, silkscreen printed over exposed copper, unconnected items, isolated zone islands, and insufficient board-edge clearance. Severity levels exist so that cosmetic issues can be distinguished from electrical ones, but downgrading a whole category to make the report go quiet is how real defects reach production. If a violation is waived, the waiver should be deliberate, limited in scope, and documented with a reason that another engineer could review later.
Refill copper zones before the final DRC pass. Zone geometry changes as tracks and vias are added, and a stale fill can hide connectivity problems or create islands that the checker will flag only after a refresh. Then run the connectivity check and confirm that every net the schematic promised actually reaches its destination on the board.
Some of the most damaging errors never appear in a DRC report at all. A footprint with the wrong pad pitch can satisfy every clearance rule while being physically impossible to assemble. Before assigning any footprint, confirm the exact manufacturer part number, compare the land pattern against the component datasheet, and verify pad pitch, pad dimensions, body outline, pin numbering, polarity, pin-1 orientation, courtyard, and solder-mask geometry. For a 0.5 mm-pitch integrated circuit, a small footprint error translates directly into an assembly defect. The datasheet land-pattern recommendation should always take precedence over an unverified community library part.
The 3D Viewer and raytracer are useful at this stage for spotting connector orientation mistakes, component collisions, and enclosure interference, but rendering is a visual aid, not mechanical validation. Critical dimensions belong against the datasheet and the enclosure drawing. If the schematic changes after layout has started, re-run ERC and re-annotate before trusting the previous DRC results.
Building a Manufacturing Package That Survives Fabrication Review
Once the board is clean, the output stage begins. KiCad can generate Gerber layers, drill files, board outlines, and supporting fabrication data, and the package should match the format the fabricator actually requests. A complete handoff normally includes copper layers, solder mask and silkscreen layers, plated and non-plated drill files, the board outline, and a fabrication note that states stack-up, surface finish, tolerances, and any special process requirements.
Cross-check the package against the design before sending it. The number of copper layers in the Gerbers should match the stack-up drawing. Drill entries should be reconciled with finished-hole requirements, since plating affects the final diameter, and annular ring should be verified on the smallest vias. Where controlled-impedance nets exist, supply a table listing each net, its target impedance, and the tolerance, all tied to a stack-up agreed with the fabricator rather than assumed from a generic default.
File naming and revision control matter more than they appear to. A consistent convention that ties every Gerber, drill file, and note to the same product revision prevents the classic failure of sending a current board outline with last week’s drill data. Open the exported files in a Gerber viewer and inspect them as the fabricator will: solder-mask registration against pads, silkscreen overlapping exposed copper, outline closure, and drill alignment against pad centers.
A clean 3D model proves nothing about manufacturability. Fabrication readiness comes from three separate steps performed in order: a DRC pass against rules that reflect the real process, a manual review of the exported files, and a design-for-manufacturing check against the fabricator’s stated capabilities. For prototype orders, confirm copper thickness, trace width and spacing, finished hole sizes, board stack-up, and any impedance requirements before release. If the quoted process differs from what the design rules assumed, correct the rules and regenerate the outputs rather than adjusting the fabrication notes to compensate.
Madrid linguist teaching in Seoul’s K-startup campus. Sara dissects multilingual branding, kimchi microbiomes, and mindful note-taking with fountain pens. She runs a weekend book-exchange café where tapas meet tteokbokki.